131 1300 0010
鬧鐘的設(shè)置優(yōu)先級(jí)要低于正常示數(shù)，所以必須在正常示數(shù)時(shí)使用鬧鐘開(kāi)關(guān)才能進(jìn)行鬧鐘的設(shè)定，而且鬧鐘的校時(shí)校分是用的2Hz的快速校時(shí)校分，更加的方便有效，因?yàn)槭窃谡Ｓ?jì)數(shù)下的鬧鐘設(shè)定，所以設(shè)定鬧鐘時(shí)時(shí)鐘依然正常的行走。鬧鐘將向報(bào)時(shí)電路輸出一個(gè)鬧鐘來(lái)了的信號(hào)，以便在報(bào)時(shí)模塊中實(shí)現(xiàn)鬧鐘的鈴聲。具體代碼如下：
module alarm(clk_2Hz,naozhong_swh,alarm_hour,alarm_min,hour,minute,hour_reg,min_reg,alarm,swh,baochi_swh);
input clk_2Hz;
input naozhong_swh,baochi_swh; //鬧鐘開(kāi)關(guān)
input alarm_hour,alarm_min;
input [1:0]swh; //防止出現(xiàn)優(yōu)先級(jí)問(wèn)題
input [5:0]hour; //時(shí)間比較
input [5:0]minute;
output reg[5:0]hour_reg;
output reg[5:0]min_reg;
output reg alarm;
always@(posedge clk_2Hz)
begin
if((naozhong_swh)&&(swh[1:0] == 'b11)&&(!baochi_swh))
begin
if(alarm_hour)
begin
if(hour_reg == 'd23)
hour_reg <= 'd0;
else
hour_reg <= hour_reg + 'd1;
end
if(alarm_min)
begin
if(min_reg == 'd59)
min_reg <= 'd0;
else
min_reg <= min_reg + 'd1;
end
end
end
always@(posedge clk_2Hz)
begin
if((hour_reg == hour)&&(min_reg == minute))
begin
alarm <= 'd1;
end
else
begin
alarm <= 'd0;
end
end
endmodule
